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HD-6408
Data Sheet March 7, 2006 FN2952.2
CMOS Asynchronous Serial Manchester Adapter (ASMA)
The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder for creating a very high speed asynchronous serial data bus. The Encoder converts serial NRZ data (typically from a shift register) to Manchester II encoded data, adding a sync pulse and parity bit. The Decoder recognizes this sync pulse and identifies it as a Command Sync or a Data Sync. The data is then decoded and shifted out in NRZ code (typically into a shift register). Finally, the parity bit is checked. If there were no Manchester or parity errors the Decoder responds with a valid word signal. The Decoder puts the Manchester code to full use to provide clock recovery and excellent noise immunity at these very high speeds. The HD-6408 can be used in many commercial applications such as security systems, environmental control systems, serial data links and many others. It utilizes a single 12 x clock and achieves data rates of up to one million bits per second with a very minimum overhead of only 4 bits out of 20, leaving 16 bits for data.
Features
* Low Bit Error Rate * Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1MBit/s * Sync Identification and Lock-In * Clock Recovery * Manchester II Encoder, Decoder * Separate Encode and Decode * Low Operating Power. . . . . . . . . . . . . . . . . . . 50mW at 5V * Single Power Supply * 24 Ld Package * Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER HD3-6408-9 PART MARKING HD3-6408-9 TEMP. RANGE (C) PACKAGE PKG. NO. E24.6 E24.6 F24.6
-40 to +85 24 Ld PDIP
Pinout
HD-6408 (DIP) TOP VIEW
VW 1 ESC 2 TD 3 SDO 4 DC 5 BZI 6 BOI 7 UDI 8 DSC 9 CDS 10 DR 11 GND 12 24 VCC 23 EC 22 SCI 21 SD 20 SS 19 EE 18 SDI 17 BOO 16 OI
d
HD3-6408-9Z HD3-6408-9Z -40 to +85 24 Ld PDIP* (Note) (Pb-Free) HD1-6408-9 HD1-6408-9 -40 to +85 24 Ld CERDIP
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
15 BZO 14 DBS 13 MR
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HD-6408 Block Diagrams
ENCODER DECODER
EC
23
/6
14 13
DR DBS MR VW
11
BIT COUNTER
1
SCI ESC SD SS
22 2
/2
BIT COUNTER TD 3 10
VALID WORD LATCH
VALID WORD TEST CIRCUIT
PARITY CHECK
21 RESET 20 SYNC PARITY 18
COUNT DECODER
CDS
SYNC LATCH
CHARACTER FORMER 19 EE
15 16 17
DC BZO OI BOO DSC
5 9
CLOCK SYNCHRONIZER
CHARACTER IDENTIFIER
NRZ OUTPUT PORT
4 SDO
6 BZI BOI UDI 7 8 TRANSITION FINDER
SDI
DATA
2
FN2952.2 March 7, 2006
HD-6408 Pin Description
PIN 1 2 3 4 5 TYPE O O O O I SYMBOL VW ESC TD SDO DC SECTION Decoder Encoder Decoder Decoder Decoder DESCRIPTION Output high indicates receipt of a VALID WORD. ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The Encoder samples SDI on the low-to-high transition of ESC. TAKE DATA output is high during receipt of data after identification of a sync pulse and two valid Manchester data bits. SERIAL DATA OUT delivers received data in correct NRZ format. DECODER CLOCK input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the Decoder. Input a frequency equal to 12X the data rate. A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative state. This pin must be held high when the Unipolar input is used. A high input should be applied to BIPOLAR ONE IN when the bus is in its positive state, this pin must be held low when the Unipolar input is used. With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition finder circuit. If not used this input must be held low. DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK / 12), synchronized by the recovered serial data stream. COMMAND/DATA SYNC output high occurs during output of decoded data which was preceded by a Command synchronizing character. A low output indicates a Data synchronizing character. A high input to DECODER RESET during a rising edge of DECODER SHIFT CLOCK resets the decoder bit counting logic to a condition ready for a new word. GROUND supply pin. A high on MASTER RESET clears the 2:1 counters in both the encoder and decoder and the / 6 counter. DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER CLOCK. BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative sense of a bipolar line driver. A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states. BIPOLAR ONE OUT is an active low output designed to drive the one or positive sense of a bipolar line driver. SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK. A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preceding cycle being completed). SYNC SELECT actuates a Command sync for an input high and data sync for an input low. SEND DATA is an active high output which enables the external source of serial data. SEND CLOCK IN is 2X the Encoder data rate. ENCODER CLOCK is the input to the 6:1 divider. VCC is the +5V power supply pin. A 0.1F decoupling capacitor from VCC (pin 24) to GND (pin 12) is recommended.
6 7 8 9 10
I I I O O
BZI BOI UDI DSC CDS
Decoder Decoder Decoder Decoder Decoder
11 12 13 14 15 16 17 18 19 20 21 22 23 24
I I I O O I O I I I O I I I
DR GND MR DBS BZO OI BOO SDI EE SS SD SCI EC VCC
Decoder Both Both Encoder Encoder Encoder Encoder Encoder Encoder Encoder Encoder Encoder Encoder Both
3
FN2952.2 March 7, 2006
HD-6408 Encoder Operation
The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SClock input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SClock by dividing the DClock. The Encoder's cycle begins when EE is high during a falling edge of ESC (1). This cycle lasts for one word length or twenty ESC periods. At the next low-to-high transition of the ESC, a high at SS input actuates a Command sync or a low will produce a Data sync for that word (2). When the Encoder is ready to accept data, the SD output will go high and remain high for sixteen ESC periods (3) - (4). During these sixteen periods the data should be clocked into the SD Input with every high-to-low transition of the ESC (3) - (4). After the sync and Manchester II encoded data are transmitted through the BOO and BZO outputs, the Encoder adds on an additional bit which is the (odd) parity for that word (5). If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time (5) as shown to prevent a consecutive word from being encoded. At any time a low on OI will force both bipolar outputs to a high state but will not affect the Encoder in any other way. To Abort the Encoder transmission a positive pulse must be applied at MR. Any time after or during this pulse, a low-tohigh transition on SCI clears the internal counters and initializes the Encoder for a new word.
TIMING SCI ESC EE
0
1
2
3
4
5
6
7
15
16
17
18
19
DON'T CARE VALID DON'T CARE
SS
SD SDI BOO
15 1ST HALF 2ND HALF 15
14 14
13 13
12 12
11
10 11
3 3
2 2
1 1
0 0 P
BZO
SYNC
SYNC
15
14
13
12
11
3
2
1
0
P
12
3
4
5
4
FN2952.2 March 7, 2006
HD-6408 Decoder Operation
The Decoder requires a single clock with a frequency of 12 times the desired data rate applied at the DClock input. The Manchester II coded data can be presented to the Decoder in one of two ways. The BOI and BZI inputs will accept data from a differential output comparator. The UDI input can only accept noninverted Manchester II coded data (e.g. from BOO of an Encoder through an inverter to UDI). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized (1), the type of sync is indicated by the CDS output. If the sync character was a command, this output will go high (2) and remain high for sixteen DSC periods (3), otherwise it will remain low. The TD output will go high and remain high (2) - (3) while the Decoder is transmitting the decoded data through SDO. The decoded data available at SDO is in a NRZ format. The DSC is provided so that the decoded bits can be shifted into an external register on every low-to-high transition of this clock (2) - (3). Note that DECODER SHIFT CLOCK may adjust its phase up until the time that TAKE DATA goes high. After all sixteen decoded bits have been transmitted (3) the data is checked for odd parity. A high on VW output (4) indicates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. VALID WORD will go low approximately 20 DECODER SHIFT CLOCK periods after it goes high if not reset low sooner by a valid sync and two valid Manchester bits as shown (1). At any time in the above sequence a high input on DR during a low-to-high transition of DSC will abort transmission and initialize the Decoder to start looking for a new sync character.
TIMING DSC BOI BZI
0
1
2
3
4
5
6
7
8
16
17
18
19
1ST HALF 2ND HALF 15 SYNC SYNC 15
14 14
13 13
12 12
11 11
10 10
2 2
1 1
0 0
P P
TD
CDS
SDO
UNDEFINED
15
14
13
12
4
3
2
1
0
VW
FROM PREVIOUS RECEPTION
12
3
4
5
FN2952.2 March 7, 2006
HD-6408
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Gates ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) CERDIP Package. . . . . . . . . . . . . . . . . 50 11 PDIP Package* . . . . . . . . . . . . . . . . . . 60 N/A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HD-6408-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
SYMBOL VIH VIL VIHC VILC II VOH VOL ICCSB ICCOP NOTE: 1. Guaranteed but not 100% tested. Logical "1" Input Voltage Logical "0" Input Voltage
VCC = 5.0V 10%, TA = -40C to +85C TEST CONDITIONS MIN 70% VCC VCC -0.5 VIN = VCC or GND, DIP Pins 5-8, 11, 13, 16, 18, 19, 20, 22, 23 IOH = -3mA IOL = 1.8mA VIN = VCC = 5.5V Outputs Open VCC = 5.5V, f = 15MHz -1.0 2.4 TYP 20% VCC GND +0.5 0.5 8.0 MAX +1.0 0.4 2 10.0 UNITS V V V V A V V mA mA
PARAMETER
Logical "1" Input Voltage (Clock) Logical "0" Input Voltage (Clock) Input Leakage Logical "1" Output Voltage Logical "0" Output Voltage Supply Current Standby Supply Current Operating (Note 1)
AC Electrical Specifications
SYMBOL ENCODER TIMING (1) (2) (3) (4) (5) (6) (7) (8) (9) FEC FESC TECR TECF FED TMR TE1 TE2 TE3
VCC = 5.0V 10%, TA = -40C to +85C TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER
Encoder Clock Frequency Send Clock Frequency Encoder Clock Rise Time Encoder Clock Fall Time Data Rate Master Reset Pulse Width Shift Clock Delay Serial Data Setup Serial Data Hold Enable Setup Enable Pulse Width Sync Setup Sync Pulse Width Send Data Delay Bipolar Output Delay
CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF
0 0 0 150 75 75 90 100 55 150 0 -
-
12 2.0 8 8 1.0 125 50 130
MHz MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns
(10) TE4 (11) TE5
(12) TE6 (13) TE7 (14) TE8 (15) TE9
6
FN2952.2 March 7, 2006
HD-6408
AC Electrical Specifications
SYMBOL (16) TE10 (17) TE11 Enable Hold Sync Hold VCC = 5.0V 10%, TA = -40C to +85C (Continued) TEST CONDITIONS CL = 50pF CL = 50pF MIN 10 95 TYP MAX UNITS ns ns
PARAMETER
DECODER TIMING (18) FDC (19) TDCR (20) TDCF (21) FDD (22) TDR (23) TDRS (24) TDRH (25) TMR (26) TD1 (27) TD2 (28) TD3 (29) TD4 (30) TD5 (31) TD6 (32) TD7 (33) TD8 (34) TD9 (35) TD10 (36) TD11 NOTE: 2. TDC = Decoder Clock Period = 1/FDC. (These parameters are guaranteed but not 100% tested). Decoder Clock Frequency Decoder Clock Rise Time Decoder Clock Fall Time Data Rate Decoder Reset Pulse Width Decoder Reset Setup Time Decoder Reset Hold Time Master Reset Pulse Width Bipolar Data Pulse Width Sync Transition Span One Zero Overlap Short Data Transition Span Long Data Transition Span Sync Delay (ON) Take Data Delay (ON) Serial Data Out Delay Sync Delay (OFF) Take Data Delay (OFF) Valid Word Delay CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF Note 2, CL = 50pF Note 2, CL = 50pF Note 2, CL = 50pF Note 2, CL = 50pF Note 2, CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF 0 0 150 75 10 150 TDC +10 -20 0 0 0 0 18TDC 6TDC 12TDC 12 8 8 1.0 TDC -10 110 110 80 110 110 110 MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Capacitance
SYMBOL CIN CO
TA = +25C PARAMETER Input Capacitance Output Capacitance TEST CONDITIONS FREQ = 1MHz, all measurements are referenced to device GND MIN TYP 15 15 MAX UNITS pF pF
7
FN2952.2 March 7, 2006
HD-6408 AC Testing Input, Output Waveform
INPUT VIH 50% VIL 50% VOH VOL
NOTE:
AC Testing: All input signals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt.
Encoder Timing
(7) TE1 TE3 (9) VALID VALID
SCI ESC SDI
TE2 (8) SC ESC EE (11) TE5 SS (12) TE6 VALID TE7 (13) ESC (14) TE8 (7) TE1 (10) TE4
TE10 (16) (17) TE11
SD
SC
(15) TE9
BOO OR BZO
8
FN2952.2 March 7, 2006
HD-6408 Decoder Timing
NOTE: UI = 0, FOR NEXT DIAGRAMS BIT PERIOD BOI TD1 (26) BIT PERIOD BIT PERIOD
BZI
TD2 (27)
TD3 (28) TD1 (26)
TD3 (28)
COMMAND SYNC
TD2 (27)
BOI TD2 (27) BZI TD1 (26)
TD1 (26) TD3 (28) TD2 (27)
(28) TD3
DATA SYNC
BOI BZI
TD1 (26) TD3 (28) TD4 (29) ONE TD5 (30) TD3 (28)
TD1 (26) TD3 (28)
(28) TD3 TD1 (26)
TD3 (28)
TD5 (30) ZERO ONE
TD4 (29)
NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS (27) UI TD2 COMMAND SYNC (27) TD2 DATA SYNC UI TD4 (29) ONE (30) TD5 ZERO TD5 (30) ONE
(27) TD2 (27) TD2 (29) TD4 (29) TD4 ONE
UI
9
FN2952.2 March 7, 2006
HD-6408 Decoder Timing
DSC (31) TD6
(Continued)
CDS TD TD7 (32)
DSC
(33) TD8 DATA BIT
SDO
DSC
(34) TD9
CDS
(35) TD10
TD
VW
(36) TD11
DSC (23) TDRS (22) TDR DR (24) TDRH
10
FN2952.2 March 7, 2006
HD-6408 Decoder Timing
DSC CDS TD7 TD (32) (31) TD6
(Continued)
DSC SDO
(33) TD8 DATA BIT
DSC CDS TD VW
(34) TD8 (35) TD10
(36) TD11
DSC DR (23) TCRS (22) TDR (24) TDRH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN2952.2 March 7, 2006

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